In simulating digital systems to verify both their functional behavior and their timing behavior, speed of simulation is one of the most important factors. One of the key ways of speeding up simulation is for the simulation to selectively trace only the activity in the model. This selective trace occurs in two dimensions. One dimension is the model. At any given simulation time, the simulator expends no effort on the parts of the model that are not changing. The other dimension is time. Ideally, the simulator only expends effort at the simulation times at which activity occurs.
To achieve these efficiencies, activity is broken down into events that occur at specific times. As the model creates these events, it is crucial that the simulator efficiently store these events for processing at the specified simulation times and efficiently retrieve them when the simulator progresses to that simulation time. Typically, data structures and algorithms that are an implementation of a time wheel are used to accomplish this. One of the features of the time wheel is its ability to give the simulator, in one operation, the entire list of all events at the next simulation time at which an event occurs.
Each slot in the time wheel represents one unit of minimum resolvable time. A modulo operation on the simulation time is used to find the proper slot in which to place an event. Simulation time is advanced by finding the next slot in the time wheel that has a non-empty event list. The order of complexity of the modulo operation is a constant in computer time. The cost of testing each empty slot is significant enough that it is important to minimize the number of empty slots. Minimization is done by choosing a minimum resolvable time that is small enough to get the desired accuracy in time, but large enough to minimize the number of empty slots. From the simulator's point of view, it is most convenient if this minimum resolvable time is known at the beginning of simulation. Otherwise, provision must be made for re-organizing the time wheel as simulation progresses. This re-organization is very expensive.
Another difficulty is deciding the size of the time wheel. It must be large enough to cover the largest delay in the model. This assures that two different times do not have to occupy the same slot in the time wheel at the same time. This can limit the size of delay that can be modeled in a given amount of computer memory. The other options are to manage different times in the same slot or to manage a separate list of events that are far in the future. Either of these last two options introduces complexity and inefficiency into the simulator.
Simulators can operate efficiently if the minimum resolvable time can be discerned at model compilation time. There is a much less efficient mode of simulation if the minimum resolvable time can vary during the simulation.
During the analog parts of the simulation, the minimum resolvable time is determined by the simulator as the time increment required to solve the algebraic-differential equations of the model accurately. At different times during simulation, the minimum resolvable time can vary by many orders of magnitude. This minimum resolvable time can sometimes act as a delay that needs to be scheduled. At the interface from analog to digital simulation, there are threshold crossings that need to be scheduled. The times of these threshold crossings are at analog time resolution.
FIG. 9 shows the sequence of steps involved in performing a simulation. At step 905, the design description is assembled. The design description includes any kind of input that describes the design to be simulated. It can include models describing physical devices and a netlist (a list of model instances and their interconnections and parameters). Models and the netlist can be expressed as text or in compiled form. At step 910, the simulatable model is assembled. This takes the design description and converts it into a collection of data structures and executable code that can be used by the core simulator to analyze the performance of the model representing the design to be simulated. At step 915, the core simulator simulates the model. The core simulator computes the performance of the mixed analog/digital model in the domains of time and frequency. Finally, at step 920, the post-processor allows the user to inspect the simulation results, for example in a graphical viewer, and to process the results according to selected criteria.
FIGS. 4A and 4B show the simulation process for simulating an analog and mixed signal digital-analog physical circuit or system. The simulation process shows where events are scheduled internal to the system. The simulation process of FIGS. 4A and 4B is akin to the simulation process specified in IEEE Standard VHDL Analog and Mixed-Signal Extensions, IEEE Std 1076.1-1999, § 12.6.4, and is similar to the simulation performed by SABER.
In FIGS. 4A and 4B, at step 405, the simulator checks to see if there are more events to simulate. If there are scheduled times remaining, then there are more events to simulate. At step 410, assuming events remain to be simulated, scheduled analog events are handled. There are three kinds of analog events: arriving at the left boundary of a discontinuity, where the model to be simulated has executed a break; arrival at the right boundary of a discontinuity; and arrival at the time of the projected analog solution. At step 415, signals are updated. Updating signals includes propagating value changes to the signals. At step 420, processes are resumed. A process is a set of procedural steps in the hardware description language provided by the user. Processes can handle user signal changes, and can assign values to a signal. Assigning a value to a signal causes an event to be scheduled. At step 425, the timeslot is checked to see if it has ended. Because events can be scheduled with a zero delay (in other words, events can be added to be simulated immediately), the timeslot must be checked before the simulator can conclude that all scheduled events have been simulated. At step 430, assuming the end of the timeslot has been reached, postponed processes are resumed. A postponed process is a special process set to execute as a time change occurs. At step 435, the simulator checks to see if an analog projection is required. An analog projection is required if the previous analog projection only projected to the current scheduled time. If an analog projection is required, at step 440 the next analog solution is projected. Finally, at step 445, the time of the next analog/digital events is retrieved.
When there is a discernible minimum resolvable time, the simulation time can be represented as an integer. But when the delay between scheduled simulation times can be both very small and very large (i.e., the minimum resolvable time can vary), the time must be represented as a real number (non-integer). This, too, affects the complexity of the time wheel.
Accordingly, a need exists for a way to control the timing of event simulation that is not dependent on a fixed minimum resolvable time, and that allows for effectively unbounded growth in the number of scheduled times for simulation events.